One of the problems that the preferred embodiment of the invention may alleviate will be explained with reference to a conventional synchronous dynamic random access memory ("SDRAM") 2 shown in FIG. 1. The operation of the SDRAM 2 is controlled by a command decoder 4 responsive to high level command signals received on a control bus 6. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, in which the "*" designates the signal as active low. The command decoder 4 generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
The SDRAM 2 includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory banks 20, 22 depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks 20, 22 is a respective row address latch 26 which stores the row address, and a row decoder 28 which decodes the row address and applies corresponding signals to one of the arrays 20 or 22.
The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20, 22. The row addresses are generated for refresh purposes by a refresh counter 30 which is controlled by a refresh controller 32. The refresh controller 32 is, in turn, controlled by the command decoder 4. More specifically, the command decoder 4 applies either a refresh command RE, an auto refresh command AR, or a self refresh command SR to the refresh controller 32. As explained below, these three commands applied to the refresh controller 32 cause the refresh controller to refresh the rows of memory cells in the arrays 20, 22 in one of three corresponding modes, namely a refresh mode, an auto refresh mode, or a self refresh mode. These modes are described in greater detail below. The commands applied to the refresh controller 32 correspond to respective combinations of the control signals applied to the command decoder 4, as also described in detail below.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. Depending on the operating mode of the SDRAM 2, the column address is either coupled through a burst counter 42 to a column address buffer 44, or to the burst counter 42 which applies a sequence of column addresses to the column address buffer 44 starting at the column address output by the address register 12. In either case, the column address buffer 44 applies a column address to a column decoder 48 which applies various column signals to corresponding sense amplifiers and associated column circuitry 50, 52 for one of the respective arrays 20, 22.
Data to be read from one of the arrays 20, 22 is coupled to the column circuitry 50, 52 for one of the arrays 20, 22, respectively. The data is then coupled to a data output register 56 which applies the data to a data bus 58. Data to be written to one of the arrays 20, 22 is coupled from the data bus 58 through a data input register 60 to the column circuitry 50, 52 where it is transferred to one of the arrays 20, 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuitry 50, 52 such as by selectively masking data to be read from the arrays 20, 22.
As mentioned above, the SDRAM 10 shown in FIG. 1 includes a refresh controller that is used to periodically refresh the memory cells in the arrays 20, 22. The refresh controller 32 operates in a variety of modes, two of which are the auto refresh mode and the self refresh mode as mentioned above. In the auto refresh mode, the refresh controller 32 causes the SDRAM 2 to address each row of memory cells in the array using the refresh counter 30 to generate the row addresses. Thus, in the auto refresh mode, it is not necessary for an external device to apply addresses to the address bus 14 of the SDRAM 2. However, the auto refresh command must be applied to the SDRAM 2 periodically and often enough to prevent the loss of data stored in the memory cells of the arrays 20, 22.
The self refresh mode is essentially the same as the auto refresh mode except that it is not necessary to periodically apply a command to the SDRAM 2 from an external device at a rate sufficient to prevent data loss. Instead, once the refresh controller 32 is placed in the self refresh mode, it automatically initiates an auto refresh with sufficient frequency to prevent the loss of data from the memory cells of the arrays 20, 22.
As mentioned above, the auto refresh command AR and self refresh command are applied to the refresh controller 32 from the command decoder. The command decoder generates the auto refresh and the self refresh command from the chip select ("CS*"), row address strobe ("RAS*"), column address strobe ("CAS*"), write enable ("WE"), and clock enable ("CKE") control signals.
The combination of control signals corresponding to the auto refresh command and the self refresh command are illustrated in FIG. 2 along with a clock signal ("CLK") which registers the appropriate command at t.sub.0. As shown in FIG. 2, the first four control signals, namely CS*, RAS*, CAS* and WE, are the same for both the auto refresh and the self refresh commands. To assert either of these commands, CS*, RAS*, and CAS* must all be active low and WE must be active high. The final control signal, CKE, determines whether the command decoder will generate an auto refresh command or a self refresh command. If CKE is high at T.sub.0, the command decoder applies an auto refresh command AR to the refresh controller 32. If CKE is low at t.sub.0, the command decoder applies a self refresh command SE to the refresh controller 32.
A particular problem encountered with higher speed SDRAMs is a difficulty in applying all of the control signals to the SDRAM 2 at the proper time. As the operating speed of SDRAMs continues to increase, the "window" during which all of the control signals must be present continues to decrease. The problem is particularly acute for control signals that are routed to a variety of SDRAMs in a system or to a variety of locations on an SDRAM because of the relatively large capacitive loading of such signals. Even though all of the control signals may be generated at the same time, signals that are capacitively loaded to a relatively large degree will be coupled with a relatively large delay. One of these signals that is capacitively loaded to a degree greater than other signals is CKE. For this reason, when the SDRAM 2 control signals attempt to cause the command generator 4 to place in the self refresh mode, the CKE signal can be delayed excessively so that it does not go low at the same time the other control signals constituting the self refresh command are active. As a result, the command generator 4 will improperly register these as a control signals auto refresh command rather than a self refresh command.
Although the problem of excessive delays has been explained with reference to the self refresh command in an SDRAM, similar problems exist for other commands in SDRAMs and other signals in other memory devices as well as in integrated circuits other than memory devices. There is therefore a need to be able to properly interpret a combination of signals even though one or more of the signals is present earlier or later than the remaining control signals.